The present invention relates to a semiconductor structure and method of manufacture, and more particularly to a method for forming contact structures.
Increasing demand of high-density low-cost non-volatile memory has driven aggressive scaling of feature sizes for flash memories. For NOR flash memory devices, the main scaling limitation has been the cell height, and the two main factors in the cell height are the drain spacing and the gate length. The drain spacing has only been scaled insignificantly as technology nodes migrate from 90 nm to 65 nm due to the complexity of the minimum spacing (pitch) in patterning one-dimensional array of the contact holes. Gate length scaling remains a challenge for the NOR flash cell due to the requirement of a high drain voltage during Channel Hot Electron (CHE) programming. The Self-Aligned Contact (SAC) structure may also have the above-described problems.
A manufacturing method of a self-aligned contact hole structure of a NOR-type flash memory of the prior art includes the following steps: depositing a dielectric layer over memory cells, performing a CMP on the dielectric layer, forming a contact hole mask, forming contact holes by dry etching, and depositing a metal layer to fill the contact holes.
In the above-described conventional manufacturing method, the drain space can be reduced by using lithography friendly line/space pitch characteristics, and the self-contact hole structure allows the drain plug to be near the gate sidewall, thereby reducing the dimension of the flash memory to a certain extent. However, the inventor has observed that, the conventional method uses dry etching to form self-aligned contact holes, which can cause undue etching to the device structure exposed to the etching, e.g., the gate sidewalls. Such damages can result in degraded device parameters, such as a lower breakdown voltage between a word line (WL) and a drain contact hole (Drain CT). Accordingly, the performance of the semiconductor device can suffer.